Field of the Invention
The present invention relates to an epitaxial layer and a corresponding fabrication method.
The present invention is explained with regard to an epitaxial layer that is used in a DRAM memory cell. For discussion purposes, the invention is described in respect of the formation of the epitaxial layer of an individual memory cell with a trench capacitor and a transistor.
Integrated circuits (ICs) or chips contain epitaxial layers for arranging and adding monocrystalline materials, such as monocrystalline silicon, for example. In addition, integrated circuits contain capacitors for the purpose of storing charge, such as, for example, a dynamic random access memory (DRAM). In this case, the charge state in the capacitor represents a data bit.
A DRAM chip contains a matrix of memory cells which are arranged in the form of rows and columns and are addressed by word lines and bit lines. The reading of data from the memory cells or the writing of data to the memory cells is realized by activating suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor comprises, inter alia, two diffusion regions isolated from one another by a channel which is driven by a gate. Depending on the direction of current flow, one diffusion region is referred to as the drain and the other as the source. The source region is connected to a bit line, the drain region is connected to the trench capacitor and the gate is connected to a word line.
By the application of suitable voltages to the gate, the transistor is controlled in such a way that a current flow between the drain region and the source region through the channel is switched on and off. The channel is usually formed in a monocrystalline silicon, in order that the pn junctions with the source region and the drain region are formed in such a way that a leakage current through the transistor in the off state is as small as possible. Monocrystalline silicon is provided on the one hand by the substrate which is generally formed in monocrystalline fashion. Monocrystalline silicon can additionally be fabricated by epitaxial growth on monocrystalline silicon in such a way that it is formed at a position on the substrate where it was not originally arranged.
The charge stored in the capacitor decreases over time on account of leakage currents. Before the charge has decreased to a level below a threshold value, the storage capacitor must be refreshed. For this reason, these memories are referred to as dynamic RAM (DRAM).
The central problem in known DRAM variants based on a trench capacitor is the production of a sufficiently large capacitance for the trench capacitor. This problem will be aggravated in future by the advancing miniaturization of semiconductor components. The increase in the integration level means that the area available per memory cell and thus the capacitance of the trench capacitor decrease ever further.
Sense amplifiers require a sufficient signal level for reliably reading out the information situated in the memory cell. The ratio of the storage capacitance to the bit line capacitance is crucial in determining the signal level. If the storage capacitance is low, said ratio may be too small for generating an adequate signal.
A lower storage capacitance likewise requires a higher refresh frequency, because the quantity of charge stored in the trench capacitor is limited by its capacitance and additionally decreases due to leakage currents. If the quantity of charge falls below a minimum quantity of charge in the storage capacitor, then it is no longer possible for the information stored therein to be read out by the connected sense amplifiers, the information is lost and read errors arise.
One way of avoiding read errors is to reduce the leakage currents. Leakage currents can be reduced on the one hand by transistors and on the other hand by dielectrics, such as the capacitor dielectric, for example. An undesirably reduced retention time can be lengthened by these measures.
Stacked capacitors or trench capacitors are usually used in DRAMs. Examples of DRAM memory cells having a trench capacitor are given in the patents U.S. Pat. No. 5,658,816, U.S. Pat. No. 4,649,625, U.S. Pat. No. 5,512,767, U.S. Pat. No. 5,641,694, U.S. Pat. No. 5,691,549, U.S. Pat. No. 5,065,273, U.S. Pat. No. 5,736,760, U.S. Pat. No. 5,744,386 and U.S. Pat. No. 5,869,868. A trench capacitor has a three-dimensional structure which is formed in a silicon substrate, for example. An increase in the capacitor electrode area and thus in the capacitance of the trench capacitor can be achieved for example by etching more deeply into the substrate and thus by deeper trenches. In this case, the increase in the capacitance of the trench capacitor does not cause the substrate surface occupied by the memory cell to be enlarged. However, this method is also limited, since the attainable etching depth of the trench capacitor depends on the trench diameter, and, during fabrication, it is only possible to attain specific, finite aspect ratios between the trench depth and trench diameter.
As the increase in the integration level advances, the substrate surface available per memory cell decreases ever further. The associated reduction in the trench diameter leads to a reduction in the capacitance of the trench capacitor. If the capacitance of the trench capacitor is dimensioned to be so low that the charge which can be stored is insufficient for entirely satisfactory readout by the sense amplifiers connected downstream, then this results in read errors.
This problem is solved for example in the publication N. C. C. Lou, IEDM 1988, page 588 et seq. by the transistor, which is usually situated next to the trench capacitor, being moved to a position situated above the trench capacitor (SEOT memory cell: self-aligned eitaxy over trench cell). As a result, the trench can take up a part of the substrate surface which is conventionally reserved for the transistor. Through this arrangement, the trench capacitor and the transistor share part of the substrate surface. This arrangement is made possible by an epitaxial layer grown above the trench capacitor. To ensure that the epitaxial layer which is to be formed above the trench capacitor is electrically insulated from the trench capacitor, there must be an insulating layer between the epitaxial layer and the trench capacitor. This means that the substrate surface on which the epitaxial layer is grown comprises monocrystalline silicon and an insulating region. The epitaxial layer is grown on the monocrystalline silicon substrate surface and at the same time grows over the insulating region from the sides with monocrystalline silicon. For example, the overgrowth of an oxide region with monocrystalline silicon is described in the abovementioned publication. Above the insulation region, the growth directions of the silicon epitaxy collide and form an epitaxial closing joint. The epitaxial closing joint does not grow together in monocrystalline fashion. What are produced, rather, are dislocations and grain boundaries which are typical of polycrystalline silicon.
What is problematic in this case is that considerable doping fluctuations can arise at the epitaxial closing joint during the overgrowth of the insulator layer. In this case, the doping of the epitaxial closing joint is usually higher than in adjacent regions. As a result, the electrical properties of the region in which the epitaxial closing joint is situated are altered in an undesirable manner.
What has a significantly more serious effect, however, is the fact that pn junctions traversed by the epitaxial closing joint can result in an increased leakage current. Since a transistor is formed in the silicon epitaxial layer, said transistor being used as a selection transistor for DRAM memory cells, leakage currents through the selection transistor must be extremely small because otherwise the DRAM memory cell discharges on account of the leakage currents and is unusable.
A further problem is constituted by the crystal defects at the epitaxial closing joint, which can propagate further in subsequent processing steps, such as thermal steps for example, and thus enlarge the damage region.